A 2D Chaotic Oscillator for Analog IC

In this paper, we have proposed the design of an analog two-dimensional (2D) discrete-time chaotic oscillator. 2D chaotic systems are studied because of their more complex chaotic behavior compared to one-dimensional (1D) chaotic systems. The already published works on 2D chaotic systems are mainly focused either on the complex analytical combinations of familiar 1D chaotic maps such as Sine map, Logistic map, Tent map, and so on, or off-the-shelf component-based analog circuits. Due to complex hardware requirements, neither of them is feasible for hardware-efficient integrated circuit (IC) implementations. To the best of our knowledge, this proposed work is the first-ever report of an analog 2D discrete-time chaotic oscillator design that is suitable for hardware-constrained IC implementations. The chaotic performance of the proposed design is analyzed with bifurcation plots, the transient response, 2D Lyapunov exponent, and correlation coefficient measurements. It is demonstrated that the proposed design exhibits promising chaotic behavior with low hardware cost. The real-world application of the proposed 2D chaotic oscillator is presented in a random number generator (RNG) design. The applicability of the RNG in cryptography is verified by passing the generated random sequence through four standard statistical tests namely, NIST, FIPS, TestU01, and Diehard

Design, Analysis, and Application of Flipped Product Chaotic System

In this paper, a novel method is proposed to build an improved 1-D discrete chaotic map called flipped product chaotic system (FPCS) by multiplying the output of one map with the output of a vertically flipped second map. Two variants, each with nine combinations, are shown with trade-off between computational cost and performance. The chaotic properties are explored using the bifurcation diagram, Lyapunov exponent, Kolmogorov entropy, and correlation coefficient. The proposed schemes offer a wider chaotic range and improved chaotic performance compared to the constituent maps and several prior works of similar nature. Wide chaotic window and improved chaotic complexity are two desired characteristics for several security applications as these two characteristics ensure enhanced design space with elevated entropic properties. We present a general Field-Programmable Gate Array (FPGA) design framework for the hardware implementation of the proposed flipped-product schemes and the results show good qualitative agreement with the numerical results from MATLAB simulation. Finally, we present a new Pseudo Random Number Generator (PRNG) using the two variants of the proposed chaotic map and validate their excellent randomness property using four standard statistical tests, namely NIST, FIPS, TestU01, and Diehard

Cascading CMOS-Based Chaotic Maps for Improved Performance and Its Application in Efficient RNG Design

We present a general framework for improving the chaotic properties of CMOS-based chaotic maps by cascading multiple maps in series. Along with two novel chaotic map topologies, we present the 45 $nm$ designs for four CMOS-based discrete-time chaotic map topologies. With the help of the bifurcation plot and three established entropy measures, namely, Lyapunov exponent, Kolmogorov entropy, and correlation coefficient, we present an extensive chaotic performance analysis on eight unique map circuits (two under each topology) to show that under certain constraints, the cascading scheme can significantly elevate the chaotic performance. The improved chaotic entropy benefits many security applications and is demonstrated using a novel random number generator (RNG) design. Unlike conventional mathematical chaotic map-based digital pseudo-random number generators (PRNG), this proposed design is not completely deterministic due to the high susceptibility of the core analog circuit to inevitable noise that renders this design closer to a true random number generator (TRNG). By leveraging the improved chaotic performance of the transistor-level cascaded maps, significantly low area and power overhead are achieved in the RNG design. The cryptographic applicability of the RNG is verified as the generated random sequences pass four standard statistical tests namely, NIST, FIPS, Diehard, and TestU01

Normalized Linearly-Combined Chaotic System: Design, Analysis, Implementation, and Application

This work presents a general framework for developing a multiparameter 1-D chaotic system for uniform and robust chaotic operation across the parameter space. This is important for diverse practical applications where parameter disturbance may cause degradation or even complete disappearance of chaotic properties. The wide uninterrupted chaotic range and improved chaotic properties are demonstrated with the aid of stability analysis, bifurcation diagram, Lyapunov exponent (LE), Kolmogorov entropy, Shannon entropy, and correlation coefficient. We also demonstrate the proposed system's amenability to cascading for further performance improvement. We introduce an efficient field-programmable gate array-based implementation and validate its chaotic properties using comparison between simulation and experimental results. Cascaded normalized linearly-combined chaotic system (NLCS) exhibits average LE, chaotic ratio, and chaotic parameter space of 1.364, 100%, and $1.1\times 10^{12}$, respectively, for 10-bit parameter values. We provide a thorough comparison of our system with prior works both in terms of performance and hardware cost. We also introduce a simple extension scheme to build 2-D robust, hyperchaotic NLCS maps. We present a novel reconfigurable multiparameter pseudorandom number generator and validate its randomness using two standard statistical tests, namely, National Institute of Standards and Technology SP 800-22 and FIPS PUB 140-2. Finally, we outline six potential applications where NLCS will be useful